What is stricking is the similarity of the findings and the challenges with what we do in Hi-Lite, despite the very different nature of the properties verified in hardware and in software, and the different techniques involved. Pages 3 and 4, they detail the additional errors found by formal verification on a codebase already simulated, with actual examples of what simulation missed and why. Very instructive. Which leads them to propose to bring together simulation and formal verification on page 5.

Interestingly, the difficulties to bring these two worlds together are the same as the ones in software: different semantics in simulation and formal verification (ex 1 p 5) and non-executable annotations (ex 2 p 5). Good thing that we insisted on the same semantics in Hi-Lite for execution and formal verification, as well as executable annotations!

]]> http://www.open-do.org/2010/12/06/case-study-can-you-afford-to-ignore-formal-analysis/feed/ 0 http://www.open-do.org/2009/10/27/agile-tour-2009/ http://www.open-do.org/2009/10/27/agile-tour-2009/#comments Tue, 27 Oct 2009 11:40:18 +0000 Florian Villoing http://www.open-do.org/?p=803 Last week I attented the Grenoble (October 20, 2009) and Valence (October 22, 2009) conferences as part of the Agile Tour 2009 series. These events were a big success and attracted more than 450 attendees! I would like to thank one more time the CARA who did a very good job at organizing these.

The presentations were of very high quality and their diversity pleased practionners as well as managers and students. All the slides are accessible on the CARA’s website (French and English).

I gave a talk in Grenoble and Valence about the infrastructure and processes we put in place at AdaCore to build and test on a daily basis all our compilation chains and accompanying technology in a Lean fashion.

I also presented the “qualification machine” we have built based on open source technology to ease the DO-178B tool qualification process by adopting an agile philosophy.